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GHz PLL with I2C Bus and Four Chip Addresses
MGP 3006X6
Bipolar IC
Features
q q q q q q
1-chip system for MPU-control (I2C Bus) 4 programmable chip addresses Short pull-in time for quick channel switch-over and optimized loop stability 3 high-current band switch outputs (20 mA) Software-compatible with SDA 3202 series Oxis III technology
P-DSO-16-1
Type MGP 3006X6 MGP 3006X6
Ordering Code Q67000-H5113 Q67006-H5113
Package P-DSO-16-1 (SMD) P-DSO-16-1 Tape & Reel (SMD)
Combined with a VCO (tuner), the MGP 3006X6 device, with four hard-switched chip addresses, forms a digitally programmable phase-locked loop for use in television sets with PLL-frequency synthesis tuning. The PLL permits precise crystal-controlled setting of the frequency of the tuner oscillator between 16 and 1300 MHz in increments of 62.5 kHz, and, with a 2.4-GHz prescaler 1/2, in the TV-SAT band in increments of 125 kHz. The tuning process is controlled by a microprocessor via an I2C Bus. The I2C Bus noise immunity has been improved by a factor of 10 compared to the SDA 3202-2, and the new crystal oscillator generates a sinusoidal signal, suppressing the higher-order harmonics, which reduces the moire noise considerably.
Semiconductor Group
1
04.93
MGP 3006X6
Circuit Description Tuning Section UHF/VHF REF The tuner signal is capacitively coupled at the UHF/VHF-input and subsequently amplified. The reference input REF should be decoupled to ground using a capacitor of low series inductance. The signal passes through an asynchronous divider with a fixed ratio of P = 8, an adjustable divider with ratio N = 256 through 32767, and is then compared in a digital frequency/phase detector to a reference frequency fREF = 7.8125 kHz. This frequency is derived from a balanced, low-impedance 4-MHz crystal oscillator (pin Q1, Q2) by dividing its output signal by Q = 512. The phase detector has two outputs UP and DOWN that drive the two current sources I+ and I- of a charge pump. If the negative edge of the divided VCO-signal appears prior to the negative edge of the reference signal, the I+ current source pulses for the duration of the phase difference. In the reverse case the I- current source pulses. PD, UD If the two signals are in phase, the charge pump output (PD) goes into the high-impedance state (PLL is locked). An active low-pass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external output transistor at UD and external RC-circuitry). The charge pump output is also switched into the high-impedance state when the control bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuitry. UD may be switched off by the control bit OS to allow external adjustments. By means of a control bit 5I the pump current can be switched between two values by software. This programmability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO-gains in the different TV-bands can be compensated, for example. P0, P1, P2 P4, P7 CAU The software-switched outputs P0, P1, P2 can be used for direct band selection (20 mA current output). P4 and P7 are general-purpose open-collector outputs. The test bit T1 = 1 switches the test signal Cy (divided input signal) to P7. Four different chip addresses can be set by appropriate connection of pin CAU.
Q1, Q2
Semiconductor Group
2
MGP 3006X6
I2C Bus Interface Data are exchanged between the processor and the PLL on the I2C Bus. SCL, SDA The clock is generated by the processor (input SCL), while pin SDA works as an input or output depending on the direction of the data (open collector; external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhances the noise immunity of the I2C Bus. The data from the processor pass through an I2C Bus control. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are high). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes low, while SCL remains high. Stop condition: SDA goes high while SCL remains high. All further information transfer takes place during SCL = low, and the data is forwarded to the control logic on the positive clock edge. The table "bit allocation" should be referred to in the following paragraph. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA-line to low (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The eighth bit is always low. In the data portion of the telegram the first bit of the first or third data byte determines whether a divider ratio or control information is to follow. In each case the second byte of the same data type or a stop condition has to follow the first byte.
VS, GND
When the supply voltage is applied a power-on reset circuit prevents the PLL from setting the SDA-line to low, which would block the bus.
Semiconductor Group
3
MGP 3006X6
Circuit Description (cont'd) Bit Allocation
MSB Address byte 1 1 0 0 0 MA1
A = Acknowledge MA0 0 A
Prog. divider Byte 1
0
n14
n13
n12
n11
n10
n9
n8
A
Prog. divider Byte 2
n7
n6
n5
n4
n3
n2
n1
n0
A
Control info. Byte 1
1
5I
T1
T0
X
X
1
OS
A
Control info. Byte 2 Divider Ratio
P7
X
X
P4
X
P2
P1
P0
A
N = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8 + 128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 2 x n1 + n0 Band Selection P0, P1, P2, P4, P7 = 1 Open-collector output is active.
Pump Current Programming 5I = 1 UD Disable OS = 1 Test Mode T1, T0 = 0, 0 T1 = 1 T0 = 1
Semiconductor Group
High current
UD is disabled.
Normal operation P3 = fREF; P4 = Cy Tristate: charge pump output PD is in high-impedance state.
4
MGP 3006X6
Chip Address Switching MA1 0 0 1 1 MA0 0 1 0 1 Voltage at CAU (0 ... 0.1) VS open-circuit (0.4 ... 0.6) VS (0.9 ... 1) VS
Telegram Examples Start-Addr-DR1-DR2-CW1-CW2-Stop Start-Addr-CW1-CW2-DR1-DR2-Stop Start-Addr-DR1-DR2-CW1-Stop Start-Addr-CW1-CW2-DR1-Stop Start-Addr-DR1-DR2-Stop Start-Addr-CW1-CW2-Stop Start-Addr-DR1-Stop Start-Addr-CW1-Stop Start Addr DR1 DR2 CW1 CW2 Stop = = = = = = = start condition address divider ratio 1st byte divider ratio 2nd byte control word 1st byte control word 2nd byte stop condition
Semiconductor Group
5
MGP 3006X6
Pin Configuration (top view)
Semiconductor Group
6
MGP 3006X6
Pin Definitions and Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol PD Q1 Q2 SDA SCL P7 P4 CAU P2 P1 P0 Function Input active filter/charge pump output Quartz crystal Quartz crystal Data input/output for I2C Bus Clock input for I2C Bus Port output (open collector) Port output (open collector) Address switch input Port output (open collector) Port output (open collector) Port output (open collector) Supply voltage Signal input Amplifier reference input Ground Output active filter
VS
UHF/VHF REF GND UD
Semiconductor Group
7
MGP 3006X6
Block Diagram
Semiconductor Group 8
MGP 3006X6
Absolute Maximum Ratings TA = - 20 to 80 C Parameter Symbol Limit Values min. Supply voltage Output PD Crystal oscillator pins Q1, Q2 Bus input/output SDA Bus input SCL Port outputs P0, P1, P2, P4, P7 Chip address switch CAU Signal input UHF/VHF Reference input REF Output active filter UD Bus output SDA Port outputs P0, P1, P2 Port outputs P4 P7 Total port output current Junction temperature Storage temperature Thermal resistance (junction to ambient) max. 6 V V V V V V V V V V mA mA mA mA mA C C K/W open collector open collector open collector open collector for VS = 0 V for VS = 0 V Unit Remarks
VS V1 V2 V4 V5 V6 V8 V13 V14 V16 I4L I9L I7L I6L
IL
- 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 -1 -1 -1 -1
VS VS
6 6 16
VS
0.3 0.3
VS
5 20 5 7 25 125
Tj Tstg Rth JA
- 40
125 125
Semiconductor Group
9
MGP 3006X6
Absolute Maximum Ratings (cont'd) TA = - 20 to 80 C Parameter Symbol Limit Values min. Operating Range Supply voltage Ambient temperature Input frequency Crystal frequency Programmable divider factor max. Unit Remarks
VS TA f13 f2 N
4.5 - 20 16 3.2 256
5.5 80 1300 4.8 32767
V C MHz (at 25 C) MHz
AC/DC Characteristics TA = - 20 to 80 C; VS = 4.5 to 5.5 V
Parameter Symbol min. Supply current Limit Values typ. 41 max. 55 mA Unit Test Condition Test Circuit 1
IS
VS = 5 V
Crystal Oscillator Connections Q1, Q2 Oscillation frequency f2 Margin from 1st (fundamental) to 2nd and 3rd harmonics1) Signal Input UHF/VHF Sensitivity 3.99975 4.000 20 4.00025 MHz dB
fQ = 4 MHz
1
a13 a13 a13
-- 27/10 -- 27/10 -- 20/22
3/315 3/315 3/315
2) dBm/ f13 = 70 ... 500 MHz 2) dBm/ f13 = 1000 MHz 2) dBm/ f13 = 1100 MHz
2 2 2
Port Outputs P0, P1, P2 (switch with open collector) H-output current L-output voltage Notes see page 11.
I9H V9L
10 0.5
A V
V6H = 13.5 V I6L = 20 mA
3 3
Semiconductor Group
10
MGP 3006X6
AC/DC Characteristics (cont'd) TA = - 20 to 80 C; VS = 4.5 to 5.5 V
Parameter Symbol min. Limit Values typ. max. Unit Test Condition Test Circuit
Port Outputs P4, P7 (switch with open collector) H-output current L-output voltage
I6H V6L
10 0.5
A V
V6H = 13.5 V I6L = 1.7 mA
4 4
Phase-Detector Output PD (VS = 5 V) Pump current Pump current Tristate current3) Current gain from PD to UD3) Output voltage
I1H I1H I1Z
2
90 22 -3 6400
220 50 1
300 75 3
A A nA
5I = 1; V1 = 2 V 5I = 0; V1 = 2 V T1 = 1; V1 = 2 V T1 = 1; V1 = 2 V; I1 = 2 nA
5 5 5 5
V1L
1.0
2.5
V
locked
5
Active Filter Output UD (Test mode T0 = 1; PD = tristate) Output current - I16 500 A 100 500 mV mV
V16 = 0.8 V; I1H = 90 A V1L = 0 V OS = 1; VS = 5 V; TA = 25 C
5
Output voltage Output voltage
V16 V16
5 5
Chip Address Switch CAU Input current Input current
I8H - I8L
50 50
A A
V8H = 5 V V8L = 5 V
7 7
1) Design note only: no 100 % final inspection. 2) mVrms into 50 . 3) Ripple voltage on tuning line (see application circuit) = 128 s (I1Z + I16/2)(C1 + C2) / (C1 C2) e.g. for I16 = 8 A, C1 = 180 nF, C2 = 9 pF, worst-case ripple voltage = 61 A.
Semiconductor Group
11
MGP 3006X6
AC/DC Characteristics TA = - 20 to 80 C; VS = 4.5 to 5.5 V; refer to test circuit 6 Parameter Symbol min. Bus Inputs SCL, SDA H-input voltage L-input voltage H-input current L-input current Limit Values typ. max. Unit Test Condition
V4IH V4IL I4IH
- I4IL
3
5.5 1.5 10 20
V V A A
V4IH = VS V4IL = 0 V
Bus Output SDA (open collector) H-output current L-output voltage Edges SCL, SDA Rise time Fall time Shift Clock SCL Frequency H-pulse width L-pulse width Start Set-up time Hold time Notes see page 19
I4OH V4OL
10 0.4
A V
V4OH = 5.5 V I4OL = 3 mA
tR tF
1 0.3
s s
f5 t5HIGH t5LOW
0 4 4.7
100
kHz s s
tSUSTA tHDSTA
4.7 4
s s
Semiconductor Group
12
MGP 3006X6
AC/DC Characteristics (cont'd) TA = - 20 to 80 C; VS = 4.5 to 5.5 V; refer to test circuit 6 Parameter Symbol min. Stop Set-up time Bus free Data Transfer Set-up time Hold time Input hysteresis SCL, SDA1) Low-pass cutoff frequency SCL, SDA1) Limit Values typ. max. Unit Test Condition
tSUSTO tBUF
4.7 4.7
s s
tSUDAT tHDDAT
0.25 0 300 500
s s mV kHz
1) Design note only: no 100 % final inspection.
Semiconductor Group
13
MGP 3006X6
Crystal Oscillator
Test Circuit 1
Semiconductor Group 14
MGP 3006X6
Calibration of Signal Generator
Measurement of Input Sensitivity
Test Circuit 2
Semiconductor Group 15
MGP 3006X6
Test Circuit 3
Test Circuit 4
Test Circuit 5
Semiconductor Group 16
MGP 3006X6
Test Circuit 6 I2C Bus Timing Diagram
Set-up time (start) Hold time (start) H-pulse width (clock) L-pulse width (clock) Set-up time (data transfer) Hold time (data transfer) Set-up time (stop) Bus free time Fall time Rise time tSUSTA tHDSTA tHIGH tLOW tSUDAT tHDDAT tSUSTO tBUF tF tR
All times related to 10 % and 90 % values. Semiconductor Group 17
MGP 3006X6
Test Circuit 7
Application Circuit
Semiconductor Group 18
MGP 3006X6
Notes 1. Loop bandwidth R = [(IP x KVCO) / (C1 x P x N)] Attenuation a = 0.5 R x R x C1 = charge pump current = VCO-gain = loop filter component values = prescaler division ratio = programmable division ratio e.g. IP = 50 A, KVCO = 18.7 MHz/V, R = 22 k, C1 = 180 nF, P = 8, N = 11520 (channel 47): R = 237 Hz, fR = 38 Hz, a = 0.47 Typically, C2 = C1/5. 2. Symmetrical capacitive coupling improves the balance of the crystal oscillator and thus reduces cross-talk. 3. High-impedance port outputs and the address selection input P3 can be decoupled from external noise with a 1 nF capacitor. 4. It is important to keep to the I2C Bus specification concerning maximum capacitance and impedance. with
IP KVCO R, C1 P N
Semiconductor Group
19
MGP 3006X6
Diagrams
Sensitivity at UHF/VHF-Input
I2C Bus Noise Immunity Sinusoidal noise pulses are applied via a coupling capacitance of 33 pF to the SCL- and SDA-inputs.
Semiconductor Group 20
MGP 3006X6
Plastic Package, P-DSO-16-1 (SMD) (Plastic Dual Small Outline)
GPS05119
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information" SMD = Surface Mounted Device Semiconductor Group 21
Dimensions in mm

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